# alexforencich/verilog-ethernet

<https://repo.masters-masters.com/en/repos/alexforencich/verilog-ethernet>

[Home](https://repo.masters-masters.com/en) › [alexforencich](https://repo.masters-masters.com/en/owners/alexforencich) › [verilog-ethernet](https://repo.masters-masters.com/en/repos/alexforencich/verilog-ethernet)

alexforencich/verilog-ethernet has 3,145 stars on GitHub. Its RepoMasters card: RC tier. Verilog Ethernet components for FPGA implementation Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [alexforencich](https://repo.masters-masters.com/en/owners/alexforencich) |
| Stars | 3,145 |
| Forks | 867 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | MIT |
| Created | 2014 |
| Tier | [RC (2,000 to 4,999 ★)](https://repo.masters-masters.com/en/ranks/blockbuster) |
| View on GitHub | [alexforencich/verilog-ethernet](https://github.com/alexforencich/verilog-ethernet) |

## Repository

Verilog Ethernet components for FPGA implementation

The tier for repos with 2,000 to 4,999 ★. Published odds per card pulled: 3%. Rarity: Epic.

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.