# alexforencich/verilog-pcie

<https://repo.masters-masters.com/en/repos/alexforencich/verilog-pcie>

[Home](https://repo.masters-masters.com/en) › [alexforencich](https://repo.masters-masters.com/en/owners/alexforencich) › [verilog-pcie](https://repo.masters-masters.com/en/repos/alexforencich/verilog-pcie)

alexforencich/verilog-pcie has 1,675 stars on GitHub. Its RepoMasters card: Beta tier. Verilog PCI express components Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [alexforencich](https://repo.masters-masters.com/en/owners/alexforencich) |
| Stars | 1,675 |
| Forks | 430 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | MIT |
| Created | 2019 |
| Tier | [Beta (700 to 1,999 ★)](https://repo.masters-masters.com/en/ranks/box_office) |
| View on GitHub | [alexforencich/verilog-pcie](https://github.com/alexforencich/verilog-pcie) |

## Repository

Verilog PCI express components

The tier for repos with 700 to 1,999 ★. Published odds per card pulled: 6%. Rarity: Rare.

## More repos by alexforencich

- [alexforencich/verilog-ethernet · ★ 3,145 · Verilog · RC](https://repo.masters-masters.com/en/repos/alexforencich/verilog-ethernet)
- [alexforencich/verilog-axi · ★ 2,168 · Verilog · RC](https://repo.masters-masters.com/en/repos/alexforencich/verilog-axi)
- [alexforencich/verilog-axis · ★ 925 · Python · Beta](https://repo.masters-masters.com/en/repos/alexforencich/verilog-axis)
- [alexforencich/verilog-i2c · ★ 731 · Verilog · Beta](https://repo.masters-masters.com/en/repos/alexforencich/verilog-i2c)
- [alexforencich/verilog-uart · ★ 591 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/alexforencich/verilog-uart)
- [alexforencich/cocotbext-axi · ★ 368 · Python · Alpha](https://repo.masters-masters.com/en/repos/alexforencich/cocotbext-axi)

## Nearby in Verilog

- [olofk/serv · ★ 1,915 · Verilog · Beta](https://repo.masters-masters.com/en/repos/olofk/serv)
- [ufrisk/pcileech-fpga · ★ 1,852 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ufrisk/pcileech-fpga)
- [ultraembedded/riscv · ★ 1,812 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ultraembedded/riscv)
- [ZipCPU/zipcpu · ★ 1,597 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ZipCPU/zipcpu)
- [XUANTIE-RV/openc910 · ★ 1,492 · Verilog · Beta](https://repo.masters-masters.com/en/repos/XUANTIE-RV/openc910)
- [aolofsson/oh · ★ 1,439 · Verilog · Beta](https://repo.masters-masters.com/en/repos/aolofsson/oh)

---
Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.