# alexforencich/verilog-uart

<https://repo.masters-masters.com/en/repos/alexforencich/verilog-uart>

[Home](https://repo.masters-masters.com/en) › [alexforencich](https://repo.masters-masters.com/en/owners/alexforencich) › [verilog-uart](https://repo.masters-masters.com/en/repos/alexforencich/verilog-uart)

alexforencich/verilog-uart has 591 stars on GitHub. Its RepoMasters card: Alpha tier. Verilog UART Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [alexforencich](https://repo.masters-masters.com/en/owners/alexforencich) |
| Stars | 591 |
| Forks | 158 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | MIT |
| Created | 2014 |
| Tier | [Alpha (250 to 699 ★)](https://repo.masters-masters.com/en/ranks/b_movie) |
| View on GitHub | [alexforencich/verilog-uart](https://github.com/alexforencich/verilog-uart) |

## Repository

Verilog UART

The tier for repos with 250 to 699 ★. Published odds per card pulled: 20%. Rarity: Uncommon.

## More repos by alexforencich

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.