# alexforencich/verilog-wishbone

<https://repo.masters-masters.com/en/repos/alexforencich/verilog-wishbone>

[Home](https://repo.masters-masters.com/en) › [alexforencich](https://repo.masters-masters.com/en/owners/alexforencich) › [verilog-wishbone](https://repo.masters-masters.com/en/repos/alexforencich/verilog-wishbone)

alexforencich/verilog-wishbone has 137 stars on GitHub. Its RepoMasters card: Prototype tier. Verilog wishbone components Language: Python.

| Field | Value |
| --- | --- |
| Owner | [alexforencich](https://repo.masters-masters.com/en/owners/alexforencich) |
| Stars | 137 |
| Forks | 37 |
| Language | [Python](https://repo.masters-masters.com/en/languages/python) |
| License | MIT |
| Created | 2013 |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [alexforencich/verilog-wishbone](https://github.com/alexforencich/verilog-wishbone) |

## Repository

Verilog wishbone components

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## More repos by alexforencich

- [alexforencich/verilog-ethernet · ★ 3,145 · Verilog · RC](https://repo.masters-masters.com/en/repos/alexforencich/verilog-ethernet)
- [alexforencich/verilog-axi · ★ 2,168 · Verilog · RC](https://repo.masters-masters.com/en/repos/alexforencich/verilog-axi)
- [alexforencich/verilog-pcie · ★ 1,675 · Verilog · Beta](https://repo.masters-masters.com/en/repos/alexforencich/verilog-pcie)
- [alexforencich/verilog-axis · ★ 925 · Python · Beta](https://repo.masters-masters.com/en/repos/alexforencich/verilog-axis)
- [alexforencich/verilog-i2c · ★ 731 · Verilog · Beta](https://repo.masters-masters.com/en/repos/alexforencich/verilog-i2c)
- [alexforencich/verilog-uart · ★ 591 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/alexforencich/verilog-uart)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.