# ash-olakangal/RISC-V-Processor

<https://repo.masters-masters.com/en/repos/ash-olakangal/RISC-V-Processor>

[Home](https://repo.masters-masters.com/en) › [ash-olakangal](https://repo.masters-masters.com/en/owners/ash-olakangal) › [RISC-V-Processor](https://repo.masters-masters.com/en/repos/ash-olakangal/RISC-V-Processor)

ash-olakangal/RISC-V-Processor has 183 stars on GitHub. Its RepoMasters card: Prototype tier. Verilog implementation of multi-stage 32-bit RISC-V processor

| Field | Value |
| --- | --- |
| Owner | [ash-olakangal](https://repo.masters-masters.com/en/owners/ash-olakangal) |
| Stars | 183 |
| Forks | 50 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | None |
| Created | 2020 |
| Topics | computer-architecture, risc-v, verilog, risc-processor |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [ash-olakangal/RISC-V-Processor](https://github.com/ash-olakangal/RISC-V-Processor) |

## Repository

Verilog implementation of multi-stage 32-bit RISC-V processor

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.