# ataradov/riscv

<https://repo.masters-masters.com/en/repos/ataradov/riscv>

[Home](https://repo.masters-masters.com/en) › [ataradov](https://repo.masters-masters.com/en/owners/ataradov) › [riscv](https://repo.masters-masters.com/en/repos/ataradov/riscv)

ataradov/riscv has 155 stars on GitHub. Its RepoMasters card: Prototype tier. Verilog implementation of a RISC-V core Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [ataradov](https://repo.masters-masters.com/en/owners/ataradov) |
| Stars | 155 |
| Forks | 21 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | BSD-3-Clause |
| Created | 2018 |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [ataradov/riscv](https://github.com/ataradov/riscv) |

## Repository

Verilog implementation of a RISC-V core

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## More repos by ataradov

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- [ataradov/open-5012h · ★ 148 · C · Prototype](https://repo.masters-masters.com/en/repos/ataradov/open-5012h)

## Nearby in Verilog

- [m-labs/milkymist · ★ 155 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/m-labs/milkymist)
- [ejrh/cpu · ★ 155 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/ejrh/cpu)
- [lnis-uofu/SOFA · ★ 155 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/lnis-uofu/SOFA)
- [danshanley/FPU · ★ 154 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/danshanley/FPU)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.