# avakar/usbcorev

<https://repo.masters-masters.com/en/repos/avakar/usbcorev>

[Home](https://repo.masters-masters.com/en) › [avakar](https://repo.masters-masters.com/en/owners/avakar) › [usbcorev](https://repo.masters-masters.com/en/repos/avakar/usbcorev)

avakar/usbcorev has 244 stars on GitHub. Its RepoMasters card: Prototype tier. A full-speed device-side USB peripheral core written in Verilog.

| Field | Value |
| --- | --- |
| Owner | [avakar](https://repo.masters-masters.com/en/owners/avakar) |
| Stars | 244 |
| Forks | 47 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | None |
| Created | 2013 |
| Topics | fpga, verilog, usb |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [avakar/usbcorev](https://github.com/avakar/usbcorev) |

## Repository

A full-speed device-side USB peripheral core written in Verilog.

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## More repos by avakar

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- [avakar/pytoml · ★ 131 · Python · Prototype](https://repo.masters-masters.com/en/repos/avakar/pytoml)

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- [efabless/caravel\_user\_project · ★ 244 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/efabless/caravel_user_project)
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- [soDLA-publishment/soDLA · ★ 241 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/soDLA-publishment/soDLA)
- [ChFrenkel/ODIN · ★ 241 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/ChFrenkel/ODIN)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.