# ben-marshall/uart

<https://repo.masters-masters.com/en/repos/ben-marshall/uart>

[Home](https://repo.masters-masters.com/en) › [ben-marshall](https://repo.masters-masters.com/en/owners/ben-marshall) › [uart](https://repo.masters-masters.com/en/repos/ben-marshall/uart)

ben-marshall/uart has 198 stars on GitHub. Its RepoMasters card: Prototype tier. A simple implementation of a UART modem in Verilog. Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [ben-marshall](https://repo.masters-masters.com/en/owners/ben-marshall) |
| Stars | 198 |
| Forks | 30 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | MIT |
| Created | 2017 |
| Topics | hardware, fpga, verilog, verilog-hdl, uart, uart-verilog |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [ben-marshall/uart](https://github.com/ben-marshall/uart) |

## Repository

A simple implementation of a UART modem in Verilog.

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## More repos by ben-marshall

- [ben-marshall/awesome-open-hardware-verification · ★ 634 · Alpha](https://repo.masters-masters.com/en/repos/ben-marshall/awesome-open-hardware-verification)
- [ben-marshall/verilog-parser · ★ 135 · C · Prototype](https://repo.masters-masters.com/en/repos/ben-marshall/verilog-parser)
- [ben-marshall/verilog-vcd-parser · ★ 104 · C++ · Prototype](https://repo.masters-masters.com/en/repos/ben-marshall/verilog-vcd-parser)

## Nearby in Verilog

- [sumanth-kalluri/cnn\_hardware\_acclerator\_for\_fpga · ★ 199 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/sumanth-kalluri/cnn_hardware_acclerator_for_fpga)
- [benreynwar/fft-dit-fpga · ★ 198 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/benreynwar/fft-dit-fpga)
- [thedatabusdotio/fpga-ml-accelerator · ★ 198 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/thedatabusdotio/fpga-ml-accelerator)
- [rejunity/tiny-asic-1\_58bit-matrix-mul · ★ 197 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/rejunity/tiny-asic-1_58bit-matrix-mul)
- [hrvach/fpg1 · ★ 195 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/hrvach/fpg1)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.