# benreynwar/fft-dit-fpga

<https://repo.masters-masters.com/en/repos/benreynwar/fft-dit-fpga>

[Home](https://repo.masters-masters.com/en) › [benreynwar](https://repo.masters-masters.com/en/owners/benreynwar) › [fft-dit-fpga](https://repo.masters-masters.com/en/repos/benreynwar/fft-dit-fpga)

benreynwar/fft-dit-fpga has 198 stars on GitHub. Its RepoMasters card: Prototype tier. Verilog module for calculation of FFT. Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [benreynwar](https://repo.masters-masters.com/en/owners/benreynwar) |
| Stars | 198 |
| Forks | 52 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | MIT |
| Created | 2012 |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [benreynwar/fft-dit-fpga](https://github.com/benreynwar/fft-dit-fpga) |

## Repository

Verilog module for calculation of FFT.

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## Nearby in Verilog

- [sumanth-kalluri/cnn\_hardware\_acclerator\_for\_fpga · ★ 199 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/sumanth-kalluri/cnn_hardware_acclerator_for_fpga)
- [ben-marshall/uart · ★ 198 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/ben-marshall/uart)
- [thedatabusdotio/fpga-ml-accelerator · ★ 198 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/thedatabusdotio/fpga-ml-accelerator)
- [rejunity/tiny-asic-1\_58bit-matrix-mul · ★ 197 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/rejunity/tiny-asic-1_58bit-matrix-mul)
- [hrvach/fpg1 · ★ 195 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/hrvach/fpg1)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.