# chenyuliu577-cyber/jyd-rv32i-fpga-core

<https://repo.masters-masters.com/en/repos/chenyuliu577-cyber/jyd-rv32i-fpga-core>

[Home](https://repo.masters-masters.com/en) › [chenyuliu577-cyber](https://repo.masters-masters.com/en/owners/chenyuliu577-cyber) › [jyd-rv32i-fpga-core](https://repo.masters-masters.com/en/repos/chenyuliu577-cyber/jyd-rv32i-fpga-core)

chenyuliu577-cyber/jyd-rv32i-fpga-core has 155 stars on GitHub. Its RepoMasters card: Prototype tier. Educational RV32I FPGA CPU/SoC project organized for JYD…

| Field | Value |
| --- | --- |
| Owner | [chenyuliu577-cyber](https://repo.masters-masters.com/en/owners/chenyuliu577-cyber) |
| Stars | 155 |
| Forks | 32 |
| Language | [SystemVerilog](https://repo.masters-masters.com/en/languages/systemverilog) |
| License | MIT |
| Created | 2026 |
| Topics | computer-architecture, contest, cpu, digital-design, education, fpga, hardware-design, riscv, rv32i, systemverilog |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [chenyuliu577-cyber/jyd-rv32i-fpga-core](https://github.com/chenyuliu577-cyber/jyd-rv32i-fpga-core) |

## Repository

Educational RV32I FPGA CPU/SoC project organized for JYD RISC-V contest-style Vivado reconstruction and verification.

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.