# chili-chips-ba/openCologne-PCIE

<https://repo.masters-masters.com/en/repos/chili-chips-ba/openCologne-PCIE>

[Home](https://repo.masters-masters.com/en) › [chili-chips-ba](https://repo.masters-masters.com/en/owners/chili-chips-ba) › [openCologne-PCIE](https://repo.masters-masters.com/en/repos/chili-chips-ba/openCologne-PCIE)

chili-chips-ba/openCologne-PCIE has 114 stars on GitHub. Its RepoMasters card: Prototype tier. The first-ever opensource soft core for PCIE EndPoint. Without…

| Field | Value |
| --- | --- |
| Owner | [chili-chips-ba](https://repo.masters-masters.com/en/owners/chili-chips-ba) |
| Stars | 114 |
| Forks | 14 |
| Language | [SystemVerilog](https://repo.masters-masters.com/en/languages/systemverilog) |
| License | BSD-3-Clause |
| Created | 2025 |
| Topics | endpoint, fpga, m2, pcb, pcie, pipe, rtl, verilog, bfm, edubos5 |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [chili-chips-ba/openCologne-PCIE](https://github.com/chili-chips-ba/openCologne-PCIE) |

## Repository

The first-ever opensource soft core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers. With standard PIPE interface for vendor SerDes. Portable, unencrypted, free SVerilog RTL with best-in-class VIP, M.2 and Edge cards for GateMate. Project opens PCIE conne…

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## More repos by chili-chips-ba

- [chili-chips-ba/wireguard-fpga · ★ 1,378 · Python · Beta](https://repo.masters-masters.com/en/repos/chili-chips-ba/wireguard-fpga)
- [chili-chips-ba/openPCIE · ★ 114 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/chili-chips-ba/openPCIE)
- [chili-chips-ba/openCologne · ★ 108 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/chili-chips-ba/openCologne)
- [chili-chips-ba/openeye-CamSI · ★ 102 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/chili-chips-ba/openeye-CamSI)

## Nearby in SystemVerilog

- [pulp-platform/hero · ★ 114 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/pulp-platform/hero)
- [chili-chips-ba/openPCIE · ★ 114 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/chili-chips-ba/openPCIE)
- [nand2mario/z8086 · ★ 114 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/nand2mario/z8086)
- [mole99/greyhound-ihp · ★ 112 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/mole99/greyhound-ihp)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.