# chili-chips-ba/openPCIE

<https://repo.masters-masters.com/en/repos/chili-chips-ba/openPCIE>

[Home](https://repo.masters-masters.com/en) › [chili-chips-ba](https://repo.masters-masters.com/en/owners/chili-chips-ba) › [openPCIE](https://repo.masters-masters.com/en/repos/chili-chips-ba/openPCIE)

chili-chips-ba/openPCIE has 114 stars on GitHub. Its RepoMasters card: Prototype tier. Peripheral Component Interconnect (PCI) has taken the Express lane long…

| Field | Value |
| --- | --- |
| Owner | [chili-chips-ba](https://repo.masters-masters.com/en/owners/chili-chips-ba) |
| Stars | 114 |
| Forks | 16 |
| Language | [SystemVerilog](https://repo.masters-masters.com/en/languages/systemverilog) |
| License | BSD-3-Clause |
| Created | 2025 |
| Topics | backplane, fpga, pcb, pcie, rp, rtl, serdes, systemverilog, edubos5, soc |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [chili-chips-ba/openPCIE](https://github.com/chili-chips-ba/openPCIE) |

## Repository

Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to Gbps SerDes. Now for the first time in opensource on the Host side too. Our project roots for the Root Port in 4 ways: \|1\| openRTL \|2\| openBFM with unique SIM and WAVE capabilities, way better than vendor's \|3\| o…

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## More repos by chili-chips-ba

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- [chili-chips-ba/openCologne-PCIE · ★ 114 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/chili-chips-ba/openCologne-PCIE)
- [chili-chips-ba/openCologne · ★ 108 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/chili-chips-ba/openCologne)
- [chili-chips-ba/openeye-CamSI · ★ 102 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/chili-chips-ba/openeye-CamSI)

## Nearby in SystemVerilog

- [pulp-platform/hero · ★ 114 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/pulp-platform/hero)
- [chili-chips-ba/openCologne-PCIE · ★ 114 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/chili-chips-ba/openCologne-PCIE)
- [nand2mario/z8086 · ★ 114 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/nand2mario/z8086)
- [mole99/greyhound-ihp · ★ 112 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/mole99/greyhound-ihp)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.
