# chipsalliance/Cores-VeeR-EH1

<https://repo.masters-masters.com/en/repos/chipsalliance/Cores-VeeR-EH1>

[Home](https://repo.masters-masters.com/en) › [chipsalliance](https://repo.masters-masters.com/en/owners/chipsalliance) › [Cores-VeeR-EH1](https://repo.masters-masters.com/en/repos/chipsalliance/Cores-VeeR-EH1)

chipsalliance/Cores-VeeR-EH1 has 971 stars on GitHub. Its RepoMasters card: Beta tier. VeeR EH1 core Language: SystemVerilog.

| Field | Value |
| --- | --- |
| Owner | [chipsalliance](https://repo.masters-masters.com/en/owners/chipsalliance) |
| Stars | 971 |
| Forks | 246 |
| Language | [SystemVerilog](https://repo.masters-masters.com/en/languages/systemverilog) |
| License | Apache-2.0 |
| Created | 2019 |
| Topics | processor, risc, riscv, risc-v, fusesoc, verilator, western-digital, open-source-hardware, rtl, fpga |
| Tier | [Beta (700 to 1,999 ★)](https://repo.masters-masters.com/en/ranks/box_office) |
| View on GitHub | [chipsalliance/Cores-VeeR-EH1](https://github.com/chipsalliance/Cores-VeeR-EH1) |

## Repository

VeeR EH1 core

The tier for repos with 700 to 1,999 ★. Published odds per card pulled: 6%. Rarity: Rare.

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Data: GitHub · Illustration: the project’s public image, pixelated by RepoMasters.