# chipsalliance/Cores-VeeR-EL2

<https://repo.masters-masters.com/en/repos/chipsalliance/Cores-VeeR-EL2>

[Home](https://repo.masters-masters.com/en) › [chipsalliance](https://repo.masters-masters.com/en/owners/chipsalliance) › [Cores-VeeR-EL2](https://repo.masters-masters.com/en/repos/chipsalliance/Cores-VeeR-EL2)

chipsalliance/Cores-VeeR-EL2 has 349 stars on GitHub. Its RepoMasters card: Alpha tier. VeeR EL2 Core Language: SystemVerilog.

| Field | Value |
| --- | --- |
| Owner | [chipsalliance](https://repo.masters-masters.com/en/owners/chipsalliance) |
| Stars | 349 |
| Forks | 116 |
| Language | [SystemVerilog](https://repo.masters-masters.com/en/languages/systemverilog) |
| License | Apache-2.0 |
| Created | 2020 |
| Topics | el2, verilator, western-digital, riscv, risc-v, processor, open-source-hardware, fusesoc, rtl, fpga |
| Tier | [Alpha (250 to 699 ★)](https://repo.masters-masters.com/en/ranks/b_movie) |
| View on GitHub | [chipsalliance/Cores-VeeR-EL2](https://github.com/chipsalliance/Cores-VeeR-EL2) |

## Repository

VeeR EL2 Core

The tier for repos with 250 to 699 ★. Published odds per card pulled: 20%. Rarity: Uncommon.

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.