# chipsalliance/Surelog

<https://repo.masters-masters.com/en/repos/chipsalliance/Surelog>

[Home](https://repo.masters-masters.com/en) › [chipsalliance](https://repo.masters-masters.com/en/owners/chipsalliance) › [Surelog](https://repo.masters-masters.com/en/repos/chipsalliance/Surelog)

chipsalliance/Surelog has 476 stars on GitHub. Its RepoMasters card: Alpha tier. SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides…

| Field | Value |
| --- | --- |
| Owner | [chipsalliance](https://repo.masters-masters.com/en/owners/chipsalliance) |
| Stars | 476 |
| Forks | 91 |
| Language | [C++](https://repo.masters-masters.com/en/languages/c-plus-plus) |
| License | Apache-2.0 |
| Created | 2019 |
| Topics | verilog, parser, python-api, parser-ast, vpi, systemverilog, preprocessor, vpi-api, vpi-standard, antlr |
| Tier | [Alpha (250 to 699 ★)](https://repo.masters-masters.com/en/ranks/b_movie) |
| View on GitHub | [chipsalliance/Surelog](https://github.com/chipsalliance/Surelog) |

## Repository

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

The tier for repos with 250 to 699 ★. Published odds per card pulled: 20%. Rarity: Uncommon.

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.