# chipsalliance/UHDM

<https://repo.masters-masters.com/en/repos/chipsalliance/UHDM>

[Home](https://repo.masters-masters.com/en) › [chipsalliance](https://repo.masters-masters.com/en/owners/chipsalliance) › [UHDM](https://repo.masters-masters.com/en/repos/chipsalliance/UHDM)

chipsalliance/UHDM has 269 stars on GitHub. Its RepoMasters card: Alpha tier. Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog…

| Field | Value |
| --- | --- |
| Owner | [chipsalliance](https://repo.masters-masters.com/en/owners/chipsalliance) |
| Stars | 269 |
| Forks | 49 |
| Language | [C++](https://repo.masters-masters.com/en/languages/c-plus-plus) |
| License | Apache-2.0 |
| Created | 2019 |
| Topics | vpi-api, vpi-interface, systemverilog, listener, serialization, ieee-standard |
| Tier | [Alpha (250 to 699 ★)](https://repo.masters-masters.com/en/ranks/b_movie) |
| View on GitHub | [chipsalliance/UHDM](https://github.com/chipsalliance/UHDM) |

## Repository

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

The tier for repos with 250 to 699 ★. Published odds per card pulled: 20%. Rarity: Uncommon.

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