# chipsalliance/VeeRwolf

<https://repo.masters-masters.com/en/repos/chipsalliance/VeeRwolf>

[Home](https://repo.masters-masters.com/en) › [chipsalliance](https://repo.masters-masters.com/en/owners/chipsalliance) › [VeeRwolf](https://repo.masters-masters.com/en/repos/chipsalliance/VeeRwolf)

chipsalliance/VeeRwolf has 343 stars on GitHub. Its RepoMasters card: Alpha tier. FuseSoC-based SoC for VeeR EH1 and EL2 Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [chipsalliance](https://repo.masters-masters.com/en/owners/chipsalliance) |
| Stars | 343 |
| Forks | 76 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | None |
| Created | 2019 |
| Topics | tools, fusesoc, swerv, veer |
| Tier | [Alpha (250 to 699 ★)](https://repo.masters-masters.com/en/ranks/b_movie) |
| View on GitHub | [chipsalliance/VeeRwolf](https://github.com/chipsalliance/VeeRwolf) |

## Repository

FuseSoC-based SoC for VeeR EH1 and EL2

The tier for repos with 250 to 699 ★. Published odds per card pulled: 20%. Rarity: Uncommon.

## More repos by chipsalliance

- [chipsalliance/chisel · ★ 4,827 · Scala · RC](https://repo.masters-masters.com/en/repos/chipsalliance/chisel)
- [chipsalliance/rocket-chip · ★ 3,895 · Scala · RC](https://repo.masters-masters.com/en/repos/chipsalliance/rocket-chip)
- [chipsalliance/verible · ★ 1,974 · C++ · Beta](https://repo.masters-masters.com/en/repos/chipsalliance/verible)
- [chipsalliance/riscv-dv · ★ 1,375 · Python · Beta](https://repo.masters-masters.com/en/repos/chipsalliance/riscv-dv)
- [chipsalliance/Cores-VeeR-EH1 · ★ 971 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/chipsalliance/Cores-VeeR-EH1)
- [chipsalliance/firrtl · ★ 748 · Scala · Beta](https://repo.masters-masters.com/en/repos/chipsalliance/firrtl)

## Nearby in Verilog

- [marmolejo/zet · ★ 345 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/marmolejo/zet)
- [jotego/jtcores · ★ 345 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/jotego/jtcores)
- [bluespec/Piccolo · ★ 343 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/bluespec/Piccolo)
- [cxdzyq1110/NPU\_on\_FPGA · ★ 338 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/cxdzyq1110/NPU_on_FPGA)
- [janestreet/asic-puzzle-2026 · ★ 338 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/janestreet/asic-puzzle-2026)
- [samitbasu/rhdl · ★ 330 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/samitbasu/rhdl)

---
Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.