# chipsalliance/chisel

<https://repo.masters-masters.com/en/repos/chipsalliance/chisel>

[Home](https://repo.masters-masters.com/en) › [chipsalliance](https://repo.masters-masters.com/en/owners/chipsalliance) › [chisel](https://repo.masters-masters.com/en/repos/chipsalliance/chisel)

chipsalliance/chisel has 4,826 stars on GitHub. Its RepoMasters card: RC tier. Chisel: A Modern Hardware Design Language Language: Scala.

| Field | Value |
| --- | --- |
| Owner | [chipsalliance](https://repo.masters-masters.com/en/owners/chipsalliance) |
| Stars | 4,826 |
| Forks | 666 |
| Language | [Scala](https://repo.masters-masters.com/en/languages/scala) |
| License | Apache-2.0 |
| Created | 2015 |
| Topics | chisel, chisel3, scala, firrtl, rtl, chip-generator, verilog |
| Tier | [RC (2,000 to 4,999 ★)](https://repo.masters-masters.com/en/ranks/blockbuster) |
| View on GitHub | [chipsalliance/chisel](https://github.com/chipsalliance/chisel) |

## Repository

Chisel: A Modern Hardware Design Language

The tier for repos with 2,000 to 4,999 ★. Published odds per card pulled: 3%. Rarity: Epic.

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- [chipsalliance/chisel-template · ★ 709 · Shell · Beta](https://repo.masters-masters.com/en/repos/chipsalliance/chisel-template)

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Data: GitHub · Illustration: the project’s public image, pixelated by RepoMasters.