# chipsalliance/f4pga-examples

<https://repo.masters-masters.com/en/repos/chipsalliance/f4pga-examples>

[Home](https://repo.masters-masters.com/en) › [chipsalliance](https://repo.masters-masters.com/en/owners/chipsalliance) › [f4pga-examples](https://repo.masters-masters.com/en/repos/chipsalliance/f4pga-examples)

chipsalliance/f4pga-examples has 290 stars on GitHub. Its RepoMasters card: Alpha tier. Example designs showing different ways to use F4PGA toolchains.

| Field | Value |
| --- | --- |
| Owner | [chipsalliance](https://repo.masters-masters.com/en/owners/chipsalliance) |
| Stars | 290 |
| Forks | 78 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | Apache-2.0 |
| Created | 2020 |
| Topics | fpga, fpga-designs, vexriscv, litex, conda-packages, symbiflow-toolchains, verilog, f4pga |
| Tier | [Alpha (250 to 699 ★)](https://repo.masters-masters.com/en/ranks/b_movie) |
| View on GitHub | [chipsalliance/f4pga-examples](https://github.com/chipsalliance/f4pga-examples) |

## Repository

Example designs showing different ways to use F4PGA toolchains.

The tier for repos with 250 to 699 ★. Published odds per card pulled: 20%. Rarity: Uncommon.

## More repos by chipsalliance

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- [chipsalliance/verible · ★ 1,974 · C++ · Beta](https://repo.masters-masters.com/en/repos/chipsalliance/verible)
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## Nearby in Verilog

- [opencomputeproject/Project-Zipline · ★ 295 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/opencomputeproject/Project-Zipline)
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- [hamsternz/DisplayPort\_Verilog · ★ 276 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/hamsternz/DisplayPort_Verilog)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.
