# chipsalliance/riscv-dv

<https://repo.masters-masters.com/en/repos/chipsalliance/riscv-dv>

[Home](https://repo.masters-masters.com/en) › [chipsalliance](https://repo.masters-masters.com/en/owners/chipsalliance) › [riscv-dv](https://repo.masters-masters.com/en/repos/chipsalliance/riscv-dv)

chipsalliance/riscv-dv has 1,375 stars on GitHub. Its RepoMasters card: Beta tier. Random instruction generator for RISC-V processor verification

| Field | Value |
| --- | --- |
| Owner | [chipsalliance](https://repo.masters-masters.com/en/owners/chipsalliance) |
| Stars | 1,375 |
| Forks | 402 |
| Language | [Python](https://repo.masters-masters.com/en/languages/python) |
| License | Apache-2.0 |
| Created | 2019 |
| Tier | [Beta (700 to 1,999 ★)](https://repo.masters-masters.com/en/ranks/box_office) |
| View on GitHub | [chipsalliance/riscv-dv](https://github.com/chipsalliance/riscv-dv) |

## Repository

Random instruction generator for RISC-V processor verification

The tier for repos with 700 to 1,999 ★. Published odds per card pulled: 6%. Rarity: Rare.

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Data: GitHub · Illustration: the project’s public image, pixelated by RepoMasters.