# chipsalliance/sv-tests

<https://repo.masters-masters.com/en/repos/chipsalliance/sv-tests>

[Home](https://repo.masters-masters.com/en) › [chipsalliance](https://repo.masters-masters.com/en/owners/chipsalliance) › [sv-tests](https://repo.masters-masters.com/en/repos/chipsalliance/sv-tests)

chipsalliance/sv-tests has 406 stars on GitHub. Its RepoMasters card: Alpha tier. Test suite designed to check compliance with the SystemVerilog standard.

| Field | Value |
| --- | --- |
| Owner | [chipsalliance](https://repo.masters-masters.com/en/owners/chipsalliance) |
| Stars | 406 |
| Forks | 108 |
| Language | [SystemVerilog](https://repo.masters-masters.com/en/languages/systemverilog) |
| License | ISC |
| Created | 2019 |
| Topics | systemverilog, symbiflow, verilog, hdl, rtl, compliance-testing |
| Tier | [Alpha (250 to 699 ★)](https://repo.masters-masters.com/en/ranks/b_movie) |
| View on GitHub | [chipsalliance/sv-tests](https://github.com/chipsalliance/sv-tests) |

## Repository

Test suite designed to check compliance with the SystemVerilog standard.

The tier for repos with 250 to 699 ★. Published odds per card pulled: 20%. Rarity: Uncommon.

## More repos by chipsalliance

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.