# chipsalliance/uvm-verilator

<https://repo.masters-masters.com/en/repos/chipsalliance/uvm-verilator>

[Home](https://repo.masters-masters.com/en) › [chipsalliance](https://repo.masters-masters.com/en/owners/chipsalliance) › [uvm-verilator](https://repo.masters-masters.com/en/repos/chipsalliance/uvm-verilator)

chipsalliance/uvm-verilator has 143 stars on GitHub. Its RepoMasters card: Prototype tier. Language: SystemVerilog.

| Field | Value |
| --- | --- |
| Owner | [chipsalliance](https://repo.masters-masters.com/en/owners/chipsalliance) |
| Stars | 143 |
| Forks | 35 |
| Language | [SystemVerilog](https://repo.masters-masters.com/en/languages/systemverilog) |
| License | Apache-2.0 |
| Created | 2020 |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [chipsalliance/uvm-verilator](https://github.com/chipsalliance/uvm-verilator) |

## Repository

No description.

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.