# chipsalliance/verible

<https://repo.masters-masters.com/en/repos/chipsalliance/verible>

[Home](https://repo.masters-masters.com/en) › [chipsalliance](https://repo.masters-masters.com/en/owners/chipsalliance) › [verible](https://repo.masters-masters.com/en/repos/chipsalliance/verible)

chipsalliance/verible has 1,974 stars on GitHub. Its RepoMasters card: Beta tier. Verible is a suite of SystemVerilog developer tools, including a parser…

| Field | Value |
| --- | --- |
| Owner | [chipsalliance](https://repo.masters-masters.com/en/owners/chipsalliance) |
| Stars | 1,974 |
| Forks | 314 |
| Language | [C++](https://repo.masters-masters.com/en/languages/c-plus-plus) |
| License | None |
| Created | 2019 |
| Topics | systemverilog, lexer, yacc, syntax-tree, linter, formatter, parser, systemverilog-parser, style-linter, hacktoberfest |
| Tier | [Beta (700 to 1,999 ★)](https://repo.masters-masters.com/en/ranks/box_office) |
| View on GitHub | [chipsalliance/verible](https://github.com/chipsalliance/verible) |

## Repository

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

The tier for repos with 700 to 1,999 ★. Published odds per card pulled: 6%. Rarity: Rare.

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Data: GitHub · Illustration: the project’s public image, pixelated by RepoMasters.