# darklife/darkriscv

<https://repo.masters-masters.com/en/repos/darklife/darkriscv>

[Home](https://repo.masters-masters.com/en) › [darklife](https://repo.masters-masters.com/en/owners/darklife) › [darkriscv](https://repo.masters-masters.com/en/repos/darklife/darkriscv)

darklife/darkriscv has 2,632 stars on GitHub. Its RepoMasters card: RC tier. opensouce RISC-V cpu core implemented in Verilog from scratch in one night\!

| Field | Value |
| --- | --- |
| Owner | [darklife](https://repo.masters-masters.com/en/owners/darklife) |
| Stars | 2,632 |
| Forks | 331 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | BSD-3-Clause |
| Created | 2018 |
| Topics | riscv, verilog, risc-v, fpga, core |
| Tier | [RC (2,000 to 4,999 ★)](https://repo.masters-masters.com/en/ranks/blockbuster) |
| View on GitHub | [darklife/darkriscv](https://github.com/darklife/darkriscv) |

## Repository

opensouce RISC-V cpu core implemented in Verilog from scratch in one night\!

The tier for repos with 2,000 to 4,999 ★. Published odds per card pulled: 3%. Rarity: Epic.

## Nearby in Verilog

- [The-OpenROAD-Project/OpenROAD · ★ 3,254 · Verilog · RC](https://repo.masters-masters.com/en/repos/The-OpenROAD-Project/OpenROAD)
- [alexforencich/verilog-ethernet · ★ 3,145 · Verilog · RC](https://repo.masters-masters.com/en/repos/alexforencich/verilog-ethernet)
- [SI-RISCV/e200\_opensource · ★ 2,855 · Verilog · RC](https://repo.masters-masters.com/en/repos/SI-RISCV/e200_opensource)
- [corundum/corundum · ★ 2,505 · Verilog · RC](https://repo.masters-masters.com/en/repos/corundum/corundum)
- [vortexgpgpu/vortex · ★ 2,378 · Verilog · RC](https://repo.masters-masters.com/en/repos/vortexgpgpu/vortex)
- [nvdla/hw · ★ 2,196 · Verilog · RC](https://repo.masters-masters.com/en/repos/nvdla/hw)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.