# drandyhaas/Haasoscope

<https://repo.masters-masters.com/en/repos/drandyhaas/Haasoscope>

[Home](https://repo.masters-masters.com/en) › [drandyhaas](https://repo.masters-masters.com/en/owners/drandyhaas) › [Haasoscope](https://repo.masters-masters.com/en/repos/drandyhaas/Haasoscope)

drandyhaas/Haasoscope has 165 stars on GitHub. Its RepoMasters card: Prototype tier. Docs, design, firmware, and software for the Haasoscope Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [drandyhaas](https://repo.masters-masters.com/en/owners/drandyhaas) |
| Stars | 165 |
| Forks | 48 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | MIT |
| Created | 2017 |
| Topics | open-hardware, open-source, data-acquisition, oscilloscope, python, eagle, altera, fpga, verilog |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [drandyhaas/Haasoscope](https://github.com/drandyhaas/Haasoscope) |

## Repository

Docs, design, firmware, and software for the Haasoscope

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## More repos by drandyhaas

- [drandyhaas/KiCadRoutingTools · ★ 734 · Python · Beta](https://repo.masters-masters.com/en/repos/drandyhaas/KiCadRoutingTools)
- [drandyhaas/HaasoscopePro · ★ 485 · FIRRTL · Alpha](https://repo.masters-masters.com/en/repos/drandyhaas/HaasoscopePro)

## Nearby in Verilog

- [lisper/cpus-caddr · ★ 166 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/lisper/cpus-caddr)
- [onchipuis/mriscv · ★ 166 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/onchipuis/mriscv)
- [regymm/quasiSoC · ★ 166 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/regymm/quasiSoC)
- [mhyousefi/MIPS-pipeline-processor · ★ 164 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/mhyousefi/MIPS-pipeline-processor)
- [ConstStrings/GoWinSDR · ★ 164 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/ConstStrings/GoWinSDR)
- [icebreaker-fpga/icebreaker-verilog-examples · ★ 162 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/icebreaker-fpga/icebreaker-verilog-examples)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.