# eliaskousk/parallella-riscv

<https://repo.masters-masters.com/en/repos/eliaskousk/parallella-riscv>

[Home](https://repo.masters-masters.com/en) › [eliaskousk](https://repo.masters-masters.com/en/owners/eliaskousk) › [parallella-riscv](https://repo.masters-masters.com/en/repos/eliaskousk/parallella-riscv)

eliaskousk/parallella-riscv has 109 stars on GitHub. Its RepoMasters card: Prototype tier. RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards

| Field | Value |
| --- | --- |
| Owner | [eliaskousk](https://repo.masters-masters.com/en/owners/eliaskousk) |
| Stars | 109 |
| Forks | 29 |
| Language | [SystemVerilog](https://repo.masters-masters.com/en/languages/systemverilog) |
| License | None |
| Created | 2016 |
| Topics | parallella, risc-v, rocket-chip, zynq, linux-kernel, zedboard, gsoc, gsoc-2016, rocket-core, petalinux |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [eliaskousk/parallella-riscv](https://github.com/eliaskousk/parallella-riscv) |

## Repository

RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## Nearby in SystemVerilog

- [trivialmips/TrivialMIPS · ★ 110 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/trivialmips/TrivialMIPS)
- [mmxsrup/axi4-interface · ★ 109 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/mmxsrup/axi4-interface)
- [Weiyet/MakerCode\_RTLChallenge · ★ 109 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/Weiyet/MakerCode_RTLChallenge)
- [spcl/pspin · ★ 108 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/spcl/pspin)
- [WangXuan95/UH-JLS · ★ 108 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/WangXuan95/UH-JLS)

---
Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.
