# eminfedar/fedar-f1-rv64im

<https://repo.masters-masters.com/en/repos/eminfedar/fedar-f1-rv64im>

[Home](https://repo.masters-masters.com/en) › [eminfedar](https://repo.masters-masters.com/en/owners/eminfedar) › [fedar-f1-rv64im](https://repo.masters-masters.com/en/repos/eminfedar/fedar-f1-rv64im)

eminfedar/fedar-f1-rv64im has 215 stars on GitHub. Its RepoMasters card: Prototype tier. 5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.

| Field | Value |
| --- | --- |
| Owner | [eminfedar](https://repo.masters-masters.com/en/owners/eminfedar) |
| Stars | 215 |
| Forks | 21 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | MIT |
| Created | 2021 |
| Topics | riscv64, riscv, riscv64im, core |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [eminfedar/fedar-f1-rv64im](https://github.com/eminfedar/fedar-f1-rv64im) |

## Repository

5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.