# exeex/edge-cores

<https://repo.masters-masters.com/en/repos/exeex/edge-cores>

[Home](https://repo.masters-masters.com/en) › [exeex](https://repo.masters-masters.com/en/owners/exeex) › [edge-cores](https://repo.masters-masters.com/en/repos/exeex/edge-cores)

exeex/edge-cores has 133 stars on GitHub. Its RepoMasters card: Prototype tier. The shortest path from PyTorch to custom ASICs. Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [exeex](https://repo.masters-masters.com/en/owners/exeex) |
| Stars | 133 |
| Forks | 8 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | Apache-2.0 |
| Created | 2026 |
| Topics | asic, compiler, cpp, torch, verilog |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [exeex/edge-cores](https://github.com/exeex/edge-cores) |

## Repository

The shortest path from PyTorch to custom ASICs.

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## Nearby in Verilog

- [AugustinJose1221/FPGA-Build · ★ 134 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/AugustinJose1221/FPGA-Build)
- [robinhedwards/UltimateCart · ★ 133 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/robinhedwards/UltimateCart)
- [ZipCPU/openarty · ★ 133 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/ZipCPU/openarty)
- [MiSTer-devel/Genesis\_MiSTer · ★ 132 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/MiSTer-devel/Genesis_MiSTer)
- [circuitgraph/circuitgraph · ★ 132 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/circuitgraph/circuitgraph)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.