# fromgof/TridentVision

<https://repo.masters-masters.com/en/repos/fromgof/TridentVision>

[Home](https://repo.masters-masters.com/en) › [fromgof](https://repo.masters-masters.com/en/owners/fromgof) › [TridentVision](https://repo.masters-masters.com/en/repos/fromgof/TridentVision)

fromgof/TridentVision has 312 stars on GitHub. Its RepoMasters card: Alpha tier. Implement yolov26m using a complete FPGA, without any C language code…

| Field | Value |
| --- | --- |
| Owner | [fromgof](https://repo.masters-masters.com/en/owners/fromgof) |
| Stars | 312 |
| Forks | 83 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | AGPL-3.0 |
| Created | 2026 |
| Tier | [Alpha (250 to 699 ★)](https://repo.masters-masters.com/en/ranks/b_movie) |
| View on GitHub | [fromgof/TridentVision](https://github.com/fromgof/TridentVision) |

## Repository

Implement yolov26m using a complete FPGA, without any C language code. Requires 160K LUTs and 386 DSP cores (based on Xilinx XC7K325T).

The tier for repos with 250 to 699 ★. Published odds per card pulled: 20%. Rarity: Uncommon.

## Nearby in Verilog

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- [Xilinx/libsystemctlm-soc · ★ 312 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/Xilinx/libsystemctlm-soc)
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- [SparcLab/OpenSERDES · ★ 309 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/SparcLab/OpenSERDES)
- [budude2/openfpga-GBC · ★ 308 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/budude2/openfpga-GBC)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.