# furrtek/SiliconRE

<https://repo.masters-masters.com/en/repos/furrtek/SiliconRE>

[Home](https://repo.masters-masters.com/en) › [furrtek](https://repo.masters-masters.com/en/owners/furrtek) › [SiliconRE](https://repo.masters-masters.com/en/repos/furrtek/SiliconRE)

furrtek/SiliconRE has 231 stars on GitHub. Its RepoMasters card: Prototype tier. Traces, schematics, and general infos about custom chips reverse-engineered…

| Field | Value |
| --- | --- |
| Owner | [furrtek](https://repo.masters-masters.com/en/owners/furrtek) |
| Stars | 231 |
| Forks | 17 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | GPL-2.0 |
| Created | 2019 |
| Topics | taito, reverse-engineering, silicon, asic, chip, arcade, decap, verilog, hdl, cpld |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [furrtek/SiliconRE](https://github.com/furrtek/SiliconRE) |

## Repository

Traces, schematics, and general infos about custom chips reverse-engineered from silicon

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## More repos by furrtek

- [furrtek/PrecIR · ★ 462 · C · Alpha](https://repo.masters-masters.com/en/repos/furrtek/PrecIR)
- [furrtek/DMG-CPU-Inside · ★ 331 · Alpha](https://repo.masters-masters.com/en/repos/furrtek/DMG-CPU-Inside)
- [furrtek/GB303 · ★ 141 · Assembly · Prototype](https://repo.masters-masters.com/en/repos/furrtek/GB303)

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- [nandland/spi-slave · ★ 234 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/nandland/spi-slave)
- [nonarkitten/amiga\_replacement\_project · ★ 234 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/nonarkitten/amiga_replacement_project)
- [gsmecher/minimax · ★ 231 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/gsmecher/minimax)
- [cameronshinn/tiny-tpu · ★ 230 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/cameronshinn/tiny-tpu)
- [Practical-UVM-Step-By-Step/Practical-UVM-Step-By-Step · ★ 229 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/Practical-UVM-Step-By-Step/Practical-UVM-Step-By-Step)
- [WangXuan95/FPGA-DDR-SDRAM · ★ 224 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-DDR-SDRAM)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.