# gt-synergy-lab/SIGMA

<https://repo.masters-masters.com/en/repos/gt-synergy-lab/SIGMA>

[Home](https://repo.masters-masters.com/en) › [gt-synergy-lab](https://repo.masters-masters.com/en/owners/gt-synergy-lab) › [SIGMA](https://repo.masters-masters.com/en/repos/gt-synergy-lab/SIGMA)

gt-synergy-lab/SIGMA has 119 stars on GitHub. Its RepoMasters card: Prototype tier. RTL implementation of Flex-DPE. Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [gt-synergy-lab](https://repo.masters-masters.com/en/owners/gt-synergy-lab) |
| Stars | 119 |
| Forks | 33 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | None |
| Created | 2020 |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [gt-synergy-lab/SIGMA](https://github.com/gt-synergy-lab/SIGMA) |

## Repository

RTL implementation of Flex-DPE.

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## Nearby in Verilog

- [spacemen3/PDP-1 · ★ 119 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/spacemen3/PDP-1)
- [Ummidichandrika/100-Days-of-RTL · ★ 119 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/Ummidichandrika/100-Days-of-RTL)
- [WangXuan95/FPGA-HDMI · ★ 119 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-HDMI)
- [freecores/8051 · ★ 118 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/freecores/8051)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.