# hkust-zhiyao/RTLLM

<https://repo.masters-masters.com/en/repos/hkust-zhiyao/RTLLM>

[Home](https://repo.masters-masters.com/en) › [hkust-zhiyao](https://repo.masters-masters.com/en/owners/hkust-zhiyao) › [RTLLM](https://repo.masters-masters.com/en/repos/hkust-zhiyao/RTLLM)

hkust-zhiyao/RTLLM has 243 stars on GitHub. Its RepoMasters card: Prototype tier. An open-source benchmark for generating design RTL with natural language

| Field | Value |
| --- | --- |
| Owner | [hkust-zhiyao](https://repo.masters-masters.com/en/owners/hkust-zhiyao) |
| Stars | 243 |
| Forks | 57 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | MIT |
| Created | 2023 |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [hkust-zhiyao/RTLLM](https://github.com/hkust-zhiyao/RTLLM) |

## Repository

An open-source benchmark for generating design RTL with natural language

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## More repos by hkust-zhiyao

- [hkust-zhiyao/RTL-Coder · ★ 330 · Python · Alpha](https://repo.masters-masters.com/en/repos/hkust-zhiyao/RTL-Coder)

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- [WangXuan95/FPGA-FixedPoint · ★ 241 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-FixedPoint)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.