# iammituraj/pequeno\_riscv

<https://repo.masters-masters.com/en/repos/iammituraj/pequeno_riscv>

[Home](https://repo.masters-masters.com/en) › [iammituraj](https://repo.masters-masters.com/en/owners/iammituraj) › [pequeno\_riscv](https://repo.masters-masters.com/en/repos/iammituraj/pequeno_riscv)

iammituraj/pequeno\_riscv has 161 stars on GitHub. Its RepoMasters card: Prototype tier. Pequeno R5 (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core…

| Field | Value |
| --- | --- |
| Owner | [iammituraj](https://repo.masters-masters.com/en/owners/iammituraj) |
| Stars | 161 |
| Forks | 15 |
| Language | [SystemVerilog](https://repo.masters-masters.com/en/languages/systemverilog) |
| License | Apache-2.0 |
| Created | 2023 |
| Topics | cpu, risc-v, rtl, fpga, systemverilog |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [iammituraj/pequeno\_riscv](https://github.com/iammituraj/pequeno_riscv) |

## Repository

Pequeno R5 (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32IM ISA.

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

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- [chipsalliance/caliptra-rtl · ★ 160 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/chipsalliance/caliptra-rtl)
- [accellera-official/uvm-core · ★ 156 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/accellera-official/uvm-core)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.
