# ic-lab-duth/RISC-V-Vector

<https://repo.masters-masters.com/en/repos/ic-lab-duth/RISC-V-Vector>

[Home](https://repo.masters-masters.com/en) › [ic-lab-duth](https://repo.masters-masters.com/en/owners/ic-lab-duth) › [RISC-V-Vector](https://repo.masters-masters.com/en/repos/ic-lab-duth/RISC-V-Vector)

ic-lab-duth/RISC-V-Vector has 147 stars on GitHub. Its RepoMasters card: Prototype tier. Vector processor for RISC-V vector ISA Language: SystemVerilog.

| Field | Value |
| --- | --- |
| Owner | [ic-lab-duth](https://repo.masters-masters.com/en/owners/ic-lab-duth) |
| Stars | 147 |
| Forks | 26 |
| Language | [SystemVerilog](https://repo.masters-masters.com/en/languages/systemverilog) |
| License | None |
| Created | 2020 |
| Topics | vector-processor, riscv, risc-v, systemverilog |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [ic-lab-duth/RISC-V-Vector](https://github.com/ic-lab-duth/RISC-V-Vector) |

## Repository

Vector processor for RISC-V vector ISA

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.