# icebreaker-fpga/icebreaker-verilog-examples

<https://repo.masters-masters.com/en/repos/icebreaker-fpga/icebreaker-verilog-examples>

[Home](https://repo.masters-masters.com/en) › [icebreaker-fpga](https://repo.masters-masters.com/en/owners/icebreaker-fpga) › [icebreaker-verilog-examples](https://repo.masters-masters.com/en/repos/icebreaker-fpga/icebreaker-verilog-examples)

icebreaker-fpga/icebreaker-verilog-examples has 162 stars on GitHub. Its RepoMasters card: Prototype tier. This repository contains small example designs that…

| Field | Value |
| --- | --- |
| Owner | [icebreaker-fpga](https://repo.masters-masters.com/en/owners/icebreaker-fpga) |
| Stars | 162 |
| Forks | 40 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | None |
| Created | 2018 |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [icebreaker-fpga/icebreaker-verilog-examples](https://github.com/icebreaker-fpga/icebreaker-verilog-examples) |

## Repository

This repository contains small example designs that can be used with the open source icestorm flow.

Archived: this repository is read-only

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## More repos by icebreaker-fpga

- [icebreaker-fpga/icebreaker · ★ 678 · Alpha](https://repo.masters-masters.com/en/repos/icebreaker-fpga/icebreaker)
- [icebreaker-fpga/icebreaker-workshop · ★ 145 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/icebreaker-fpga/icebreaker-workshop)

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- [TimRudy/ice-chips-verilog · ★ 160 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/TimRudy/ice-chips-verilog)
- [zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial · ★ 160 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.