# jamieiles/oldland-cpu

<https://repo.masters-masters.com/en/repos/jamieiles/oldland-cpu>

[Home](https://repo.masters-masters.com/en) › [jamieiles](https://repo.masters-masters.com/en/owners/jamieiles) › [oldland-cpu](https://repo.masters-masters.com/en/repos/jamieiles/oldland-cpu)

jamieiles/oldland-cpu has 128 stars on GitHub. Its RepoMasters card: Prototype tier. Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools

| Field | Value |
| --- | --- |
| Owner | [jamieiles](https://repo.masters-masters.com/en/owners/jamieiles) |
| Stars | 128 |
| Forks | 20 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | None |
| Created | 2013 |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [jamieiles/oldland-cpu](https://github.com/jamieiles/oldland-cpu) |

## Repository

Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## More repos by jamieiles

- [jamieiles/80x86 · ★ 422 · C++ · Alpha](https://repo.masters-masters.com/en/repos/jamieiles/80x86)
- [jamieiles/uart · ★ 203 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/jamieiles/uart)

## Nearby in Verilog

- [BerkeleyLab/Bedrock · ★ 128 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/BerkeleyLab/Bedrock)
- [jjejdhhd/License-Plate-Recognition-FPGA · ★ 128 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/jjejdhhd/License-Plate-Recognition-FPGA)
- [nand2mario/486tang · ★ 128 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/nand2mario/486tang)
- [cliffordwolf/PonyLink · ★ 128 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/cliffordwolf/PonyLink)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.
