# jasonlin316/RISC-V-CPU

<https://repo.masters-masters.com/en/repos/jasonlin316/RISC-V-CPU>

[Home](https://repo.masters-masters.com/en) › [jasonlin316](https://repo.masters-masters.com/en/owners/jasonlin316) › [RISC-V-CPU](https://repo.masters-masters.com/en/repos/jasonlin316/RISC-V-CPU)

jasonlin316/RISC-V-CPU has 153 stars on GitHub. Its RepoMasters card: Prototype tier. A RISC-V 5-stage pipelined CPU that supports vector instructions…

| Field | Value |
| --- | --- |
| Owner | [jasonlin316](https://repo.masters-masters.com/en/owners/jasonlin316) |
| Stars | 153 |
| Forks | 28 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | None |
| Created | 2019 |
| Topics | risc-v, riscv32, gate-level, place-and-route, vector, processor, chip, tape-out, verilog |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [jasonlin316/RISC-V-CPU](https://github.com/jasonlin316/RISC-V-CPU) |

## Repository

A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.