# jmahler/mips-cpu

<https://repo.masters-masters.com/en/repos/jmahler/mips-cpu>

[Home](https://repo.masters-masters.com/en) › [jmahler](https://repo.masters-masters.com/en/owners/jmahler) › [mips-cpu](https://repo.masters-masters.com/en/repos/jmahler/mips-cpu)

jmahler/mips-cpu has 660 stars on GitHub. Its RepoMasters card: Alpha tier. MIPS CPU implemented in Verilog Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [jmahler](https://repo.masters-masters.com/en/owners/jmahler) |
| Stars | 660 |
| Forks | 190 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | GPL-3.0 |
| Created | 2013 |
| Tier | [Alpha (250 to 699 ★)](https://repo.masters-masters.com/en/ranks/b_movie) |
| View on GitHub | [jmahler/mips-cpu](https://github.com/jmahler/mips-cpu) |

## Repository

MIPS CPU implemented in Verilog

The tier for repos with 250 to 699 ★. Published odds per card pulled: 20%. Rarity: Uncommon.

## Nearby in Verilog

- [antonblanchard/microwatt · ★ 730 · Verilog · Beta](https://repo.masters-masters.com/en/repos/antonblanchard/microwatt)
- [OpenTimer/OpenTimer · ★ 722 · Verilog · Beta](https://repo.masters-masters.com/en/repos/OpenTimer/OpenTimer)
- [ZipCPU/wb2axip · ★ 714 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ZipCPU/wb2axip)
- [fguzman82/gateGPT · ★ 656 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/fguzman82/gateGPT)
- [ultraembedded/core\_ddr3\_controller · ★ 646 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/ultraembedded/core_ddr3_controller)
- [dtysky/FPGA-Imaging-Library · ★ 644 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/dtysky/FPGA-Imaging-Library)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.