# keplertech/naja

<https://repo.masters-masters.com/en/repos/keplertech/naja>

[Home](https://repo.masters-masters.com/en) › [keplertech](https://repo.masters-masters.com/en/owners/keplertech) › [naja](https://repo.masters-masters.com/en/repos/keplertech/naja)

keplertech/naja has 169 stars on GitHub. Its RepoMasters card: Prototype tier. Open-source EDA framework for RTL elaboration, netlist analysis, and…

| Field | Value |
| --- | --- |
| Owner | [keplertech](https://repo.masters-masters.com/en/owners/keplertech) |
| Stars | 169 |
| Forks | 26 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | Apache-2.0 |
| Created | 2021 |
| Topics | netlist, eda, semiconductor, verilog, asic, fpga, cpp, vhdl |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [keplertech/naja](https://github.com/keplertech/naja) |

## Repository

Open-source EDA framework for RTL elaboration, netlist analysis, and transformation, with C++ and Python APIs

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## More repos by keplertech

- [keplertech/kepler-formal · ★ 114 · C++ · Prototype](https://repo.masters-masters.com/en/repos/keplertech/kepler-formal)

## Nearby in Verilog

- [liuqdev/8-bits-RISC-CPU-Verilog · ★ 169 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/liuqdev/8-bits-RISC-CPU-Verilog)
- [dan-rodrigues/icestation-32 · ★ 169 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/dan-rodrigues/icestation-32)
- [padhi499/Image-Classification-using-CNN-on-FPGA · ★ 169 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/padhi499/Image-Classification-using-CNN-on-FPGA)
- [andres-mancera/ethernet\_10ge\_mac\_SV\_UVM\_tb · ★ 168 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/andres-mancera/ethernet_10ge_mac_SV_UVM_tb)

---
Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.