# kunalg123/vsdflow

<https://repo.masters-masters.com/en/repos/kunalg123/vsdflow>

[Home](https://repo.masters-masters.com/en) › [kunalg123](https://repo.masters-masters.com/en/owners/kunalg123) › [vsdflow](https://repo.masters-masters.com/en/repos/kunalg123/vsdflow)

kunalg123/vsdflow has 170 stars on GitHub. Its RepoMasters card: Prototype tier. VSDFLOW is an automated solution to programmers, hobbyists and small scale…

| Field | Value |
| --- | --- |
| Owner | [kunalg123](https://repo.masters-masters.com/en/owners/kunalg123) |
| Stars | 170 |
| Forks | 62 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | Apache-2.0 |
| Created | 2017 |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [kunalg123/vsdflow](https://github.com/kunalg123/vsdflow) |

## Repository

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL i…

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## Nearby in Verilog

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- [dan-rodrigues/icestation-32 · ★ 169 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/dan-rodrigues/icestation-32)
- [padhi499/Image-Classification-using-CNN-on-FPGA · ★ 169 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/padhi499/Image-Classification-using-CNN-on-FPGA)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.
