# lakshmi-sathi/avsdpll\_1v8

<https://repo.masters-masters.com/en/repos/lakshmi-sathi/avsdpll_1v8>

[Home](https://repo.masters-masters.com/en) › [lakshmi-sathi](https://repo.masters-masters.com/en/owners/lakshmi-sathi) › [avsdpll\_1v8](https://repo.masters-masters.com/en/repos/lakshmi-sathi/avsdpll_1v8)

lakshmi-sathi/avsdpll\_1v8 has 126 stars on GitHub. Its RepoMasters card: Prototype tier. 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to…

| Field | Value |
| --- | --- |
| Owner | [lakshmi-sathi](https://repo.masters-masters.com/en/owners/lakshmi-sathi) |
| Stars | 126 |
| Forks | 40 |
| Language | No language |
| License | GPL-2.0 |
| Created | 2020 |
| Topics | pll, clock-multiplier, intellectual-property, analog-circuit, phase-detector, charge-pump, rtl2gds, manufacturable, ic, asic |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [lakshmi-sathi/avsdpll\_1v8](https://github.com/lakshmi-sathi/avsdpll_1v8) |

## Repository

8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.