# lauchinyuan/FPGA\_QPSK-modem

<https://repo.masters-masters.com/en/repos/lauchinyuan/FPGA_QPSK-modem>

[Home](https://repo.masters-masters.com/en) › [lauchinyuan](https://repo.masters-masters.com/en/owners/lauchinyuan) › [FPGA\_QPSK-modem](https://repo.masters-masters.com/en/repos/lauchinyuan/FPGA_QPSK-modem)

lauchinyuan/FPGA\_QPSK-modem has 253 stars on GitHub. Its RepoMasters card: Alpha tier. A QPSK modem written in the Verilog hardware description language, that…

| Field | Value |
| --- | --- |
| Owner | [lauchinyuan](https://repo.masters-masters.com/en/owners/lauchinyuan) |
| Stars | 253 |
| Forks | 46 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | None |
| Created | 2023 |
| Topics | fpga, matlab, qpsk, verilog, vivado |
| Tier | [Alpha (250 to 699 ★)](https://repo.masters-masters.com/en/ranks/b_movie) |
| View on GitHub | [lauchinyuan/FPGA\_QPSK-modem](https://github.com/lauchinyuan/FPGA_QPSK-modem) |

## Repository

A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA

The tier for repos with 250 to 699 ★. Published odds per card pulled: 20%. Rarity: Uncommon.

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- [GuoningHuang/FPGA-CNN-accelerator-based-on-systolic-array · ★ 248 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/GuoningHuang/FPGA-CNN-accelerator-based-on-systolic-array)
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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.
