# liuqdev/8-bits-RISC-CPU-Verilog

<https://repo.masters-masters.com/en/repos/liuqdev/8-bits-RISC-CPU-Verilog>

[Home](https://repo.masters-masters.com/en) › [liuqdev](https://repo.masters-masters.com/en/owners/liuqdev) › [8-bits-RISC-CPU-Verilog](https://repo.masters-masters.com/en/repos/liuqdev/8-bits-RISC-CPU-Verilog)

liuqdev/8-bits-RISC-CPU-Verilog has 169 stars on GitHub. Its RepoMasters card: Prototype tier. Architecture and Verilog Implementation of 8-bits RISC CPU…

| Field | Value |
| --- | --- |
| Owner | [liuqdev](https://repo.masters-masters.com/en/owners/liuqdev) |
| Stars | 169 |
| Forks | 42 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | MIT |
| Created | 2019 |
| Topics | verilog, fsm, risc, cpu |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [liuqdev/8-bits-RISC-CPU-Verilog](https://github.com/liuqdev/8-bits-RISC-CPU-Verilog) |

## Repository

Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.