# lowRISC/lowrisc-chip

<https://repo.masters-masters.com/en/repos/lowRISC/lowrisc-chip>

[Home](https://repo.masters-masters.com/en) › [lowRISC](https://repo.masters-masters.com/en/owners/lowRISC) › [lowrisc-chip](https://repo.masters-masters.com/en/repos/lowRISC/lowrisc-chip)

lowRISC/lowrisc-chip has 601 stars on GitHub. Its RepoMasters card: Alpha tier. The root repo for lowRISC project and FPGA demos. Language: SystemVerilog.

| Field | Value |
| --- | --- |
| Owner | [lowRISC](https://repo.masters-masters.com/en/owners/lowRISC) |
| Stars | 601 |
| Forks | 147 |
| Language | [SystemVerilog](https://repo.masters-masters.com/en/languages/systemverilog) |
| License | None |
| Created | 2015 |
| Tier | [Alpha (250 to 699 ★)](https://repo.masters-masters.com/en/ranks/b_movie) |
| View on GitHub | [lowRISC/lowrisc-chip](https://github.com/lowRISC/lowrisc-chip) |

## Repository

The root repo for lowRISC project and FPGA demos.

The tier for repos with 250 to 699 ★. Published odds per card pulled: 20%. Rarity: Uncommon.

## More repos by lowRISC

- [lowRISC/opentitan · ★ 3,728 · SystemVerilog · RC](https://repo.masters-masters.com/en/repos/lowRISC/opentitan)
- [lowRISC/ibex · ★ 2,150 · SystemVerilog · RC](https://repo.masters-masters.com/en/repos/lowRISC/ibex)
- [lowRISC/style-guides · ★ 553 · Alpha](https://repo.masters-masters.com/en/repos/lowRISC/style-guides)
- [lowRISC/riscv-llvm · ★ 279 · Shell · Alpha](https://repo.masters-masters.com/en/repos/lowRISC/riscv-llvm)
- [lowRISC/muntjac · ★ 124 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/lowRISC/muntjac)
- [lowRISC/ibex-demo-system · ★ 106 · C · Prototype](https://repo.masters-masters.com/en/repos/lowRISC/ibex-demo-system)

## Nearby in SystemVerilog

- [raysalemi/uvmprimer · ★ 657 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/raysalemi/uvmprimer)
- [openhwfoundation/cvfpu · ★ 648 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/openhwfoundation/cvfpu)
- [trivialmips/nontrivial-mips · ★ 609 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/trivialmips/nontrivial-mips)
- [pulp-platform/pulp · ★ 573 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/pulp-platform/pulp)
- [pulp-platform/pulpissimo · ★ 504 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/pulp-platform/pulpissimo)
- [dpretet/async\_fifo · ★ 498 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/dpretet/async_fifo)

---
Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.
