# lvd2/ay-3-8910\_reverse\_engineered

<https://repo.masters-masters.com/en/repos/lvd2/ay-3-8910_reverse_engineered>

[Home](https://repo.masters-masters.com/en) › [lvd2](https://repo.masters-masters.com/en/owners/lvd2) › [ay-3-8910\_reverse\_engineered](https://repo.masters-masters.com/en/repos/lvd2/ay-3-8910_reverse_engineered)

lvd2/ay-3-8910\_reverse\_engineered has 106 stars on GitHub. Its RepoMasters card: Prototype tier. The reverse-engineered AY-3-8910 chip. Transistor-level…

| Field | Value |
| --- | --- |
| Owner | [lvd2](https://repo.masters-masters.com/en/owners/lvd2) |
| Stars | 106 |
| Forks | 11 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | GPL-3.0 |
| Created | 2019 |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [lvd2/ay-3-8910\_reverse\_engineered](https://github.com/lvd2/ay-3-8910_reverse_engineered) |

## Repository

The reverse-engineered AY-3-8910 chip. Transistor-level schematics, verilog model and a testbench with tools, that can render register dump files into .flac soundtrack.

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## Nearby in Verilog

- [cavnex/mc6809 · ★ 106 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/cavnex/mc6809)
- [ZipCPU/sdr · ★ 106 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/ZipCPU/sdr)
- [WangXuan95/FPGA-RMII-SMII · ★ 106 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-RMII-SMII)
- [m-labs/lm32 · ★ 105 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/m-labs/lm32)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.