# lvyufeng/step\_into\_mips

<https://repo.masters-masters.com/en/repos/lvyufeng/step_into_mips>

[Home](https://repo.masters-masters.com/en) › [lvyufeng](https://repo.masters-masters.com/en/owners/lvyufeng) › [step\_into\_mips](https://repo.masters-masters.com/en/repos/lvyufeng/step_into_mips)

lvyufeng/step\_into\_mips has 886 stars on GitHub. Its RepoMasters card: Beta tier. 一步一步写MIPS CPU Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [lvyufeng](https://repo.masters-masters.com/en/owners/lvyufeng) |
| Stars | 886 |
| Forks | 162 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | MIT |
| Created | 2018 |
| Topics | mips-cpu, nscscc, verilog |
| Tier | [Beta (700 to 1,999 ★)](https://repo.masters-masters.com/en/ranks/box_office) |
| View on GitHub | [lvyufeng/step\_into\_mips](https://github.com/lvyufeng/step_into_mips) |

## Repository

一步一步写MIPS CPU

The tier for repos with 700 to 1,999 ★. Published odds per card pulled: 6%. Rarity: Rare.

## More repos by lvyufeng

- [lvyufeng/mindspore-nlp-tutorial · ★ 141 · Jupyter Notebook · Prototype](https://repo.masters-masters.com/en/repos/lvyufeng/mindspore-nlp-tutorial)

## Nearby in Verilog

- [WangXuan95/FPGA-USB-Device · ★ 934 · Verilog · Beta](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-USB-Device)
- [open-sdr/openwifi-hw · ★ 917 · Verilog · Beta](https://repo.masters-masters.com/en/repos/open-sdr/openwifi-hw)
- [FeSens/openTPU · ★ 907 · Verilog · Beta](https://repo.masters-masters.com/en/repos/FeSens/openTPU)
- [KastnerRG/riffa · ★ 884 · Verilog · Beta](https://repo.masters-masters.com/en/repos/KastnerRG/riffa)
- [Obijuan/open-fpga-verilog-tutorial · ★ 871 · Verilog · Beta](https://repo.masters-masters.com/en/repos/Obijuan/open-fpga-verilog-tutorial)
- [xiaop1/Verilog-Practice · ★ 818 · Verilog · Beta](https://repo.masters-masters.com/en/repos/xiaop1/Verilog-Practice)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.
