# maltanar/fpga-tidbits

<https://repo.masters-masters.com/en/repos/maltanar/fpga-tidbits>

[Home](https://repo.masters-masters.com/en) › [maltanar](https://repo.masters-masters.com/en/owners/maltanar) › [fpga-tidbits](https://repo.masters-masters.com/en/repos/maltanar/fpga-tidbits)

maltanar/fpga-tidbits has 129 stars on GitHub. Its RepoMasters card: Prototype tier. Chisel components for FPGA projects Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [maltanar](https://repo.masters-masters.com/en/owners/maltanar) |
| Stars | 129 |
| Forks | 29 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | BSD-2-Clause |
| Created | 2015 |
| Topics | fpga, chisel, hardware-libraries |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [maltanar/fpga-tidbits](https://github.com/maltanar/fpga-tidbits) |

## Repository

Chisel components for FPGA projects

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## Nearby in Verilog

- [freecores/dma\_axi · ★ 130 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/freecores/dma_axi)
- [Herooyyy/Free-DMA-Firmware-pcileech · ★ 130 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/Herooyyy/Free-DMA-Firmware-pcileech)
- [opengateware/openFPGA-Genesis · ★ 129 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/opengateware/openFPGA-Genesis)
- [jamieiles/oldland-cpu · ★ 128 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/jamieiles/oldland-cpu)
- [cliffordwolf/PonyLink · ★ 128 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/cliffordwolf/PonyLink)
- [PulseRain/Reindeer · ★ 128 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/PulseRain/Reindeer)

---
Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.