# marcoz001/axi-uvm

<https://repo.masters-masters.com/en/repos/marcoz001/axi-uvm>

[Home](https://repo.masters-masters.com/en) › [marcoz001](https://repo.masters-masters.com/en/owners/marcoz001) › [axi-uvm](https://repo.masters-masters.com/en/repos/marcoz001/axi-uvm)

marcoz001/axi-uvm has 140 stars on GitHub. Its RepoMasters card: Prototype tier. yet another AXI testbench repo. ;) This is for my UVM practice…

| Field | Value |
| --- | --- |
| Owner | [marcoz001](https://repo.masters-masters.com/en/owners/marcoz001) |
| Stars | 140 |
| Forks | 59 |
| Language | [SystemVerilog](https://repo.masters-masters.com/en/languages/systemverilog) |
| License | LGPL-3.0 |
| Created | 2017 |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [marcoz001/axi-uvm](https://github.com/marcoz001/axi-uvm) |

## Repository

yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## Nearby in SystemVerilog

- [chipsalliance/uvm-verilator · ★ 143 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/chipsalliance/uvm-verilator)
- [pulp-platform/register\_interface · ★ 142 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/pulp-platform/register_interface)
- [openhwfoundation/cva5 · ★ 140 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/openhwfoundation/cva5)
- [MiSTer-devel/C64\_MiSTer · ★ 139 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/MiSTer-devel/C64_MiSTer)
- [microsoft/cheriot-ibex · ★ 138 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/microsoft/cheriot-ibex)
- [ZcashFoundation/zcash-fpga · ★ 135 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/ZcashFoundation/zcash-fpga)

---
Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.