# mirseo/JSilicon

<https://repo.masters-masters.com/en/repos/mirseo/JSilicon>

[Home](https://repo.masters-masters.com/en) › [mirseo](https://repo.masters-masters.com/en/owners/mirseo) › [JSilicon](https://repo.masters-masters.com/en/repos/mirseo/JSilicon)

mirseo/JSilicon has 101 stars on GitHub. Its RepoMasters card: Prototype tier. JSilicon: A dual-mode 8-bit CPU core designed entirely from scratch by an AI…

| Field | Value |
| --- | --- |
| Owner | [mirseo](https://repo.masters-masters.com/en/owners/mirseo) |
| Stars | 101 |
| Forks | 10 |
| Language | [SystemVerilog](https://repo.masters-masters.com/en/languages/systemverilog) |
| License | Apache-2.0 |
| Created | 2025 |
| Topics | alu, asic, chip-design, finite-state-machine, rtl, rtl-design, verilog, control-logic, digital-designs, open-source-hardware |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [mirseo/JSilicon](https://github.com/mirseo/JSilicon) |

## Repository

JSilicon: A dual-mode 8-bit CPU core designed entirely from scratch by an AI major during mandatory military service in South Korea. This open-source Verilog project proves that real silicon design — from ALU to CPU architecture — is possible even under the most extreme constraints.

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## Nearby in SystemVerilog

- [pulp-platform/tech\_cells\_generic · ★ 102 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/pulp-platform/tech_cells_generic)
- [chili-chips-ba/openeye-CamSI · ★ 102 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/chili-chips-ba/openeye-CamSI)
- [pavona/pavona · ★ 101 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/pavona/pavona)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.