# mmxsrup/axi4-interface

<https://repo.masters-masters.com/en/repos/mmxsrup/axi4-interface>

[Home](https://repo.masters-masters.com/en) › [mmxsrup](https://repo.masters-masters.com/en/owners/mmxsrup) › [axi4-interface](https://repo.masters-masters.com/en/repos/mmxsrup/axi4-interface)

mmxsrup/axi4-interface has 109 stars on GitHub. Its RepoMasters card: Prototype tier. AXI4 and AXI4-Lite interface definitions Language: SystemVerilog.

| Field | Value |
| --- | --- |
| Owner | [mmxsrup](https://repo.masters-masters.com/en/owners/mmxsrup) |
| Stars | 109 |
| Forks | 28 |
| Language | [SystemVerilog](https://repo.masters-masters.com/en/languages/systemverilog) |
| License | GPL-3.0 |
| Created | 2019 |
| Topics | axi4, axi4-lite, fpga, systemverilog, axi4-stream |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [mmxsrup/axi4-interface](https://github.com/mmxsrup/axi4-interface) |

## Repository

AXI4 and AXI4-Lite interface definitions

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.